blob: f737ca9264640b068526b3e9650b2aee098b63e1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY send_mux_test IS
END send_mux_test;
ARCHITECTURE behavior OF send_mux_test IS
COMPONENT send_mux
PORT(
wr_clk : IN std_logic;
wr_buff : IN std_logic_vector(3 downto 0);
wr_en : IN std_logic;
wr_data : IN std_logic_vector(63 downto 0);
wr_done : IN std_logic;
wr_accept : OUT std_logic_vector(15 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
rd_data : OUT std_logic_vector(63 downto 0);
rd_valid : OUT std_logic
);
END COMPONENT;
signal wr_clk : std_logic := '0';
signal wr_buff : std_logic_vector(3 downto 0) := (others => '0');
signal wr_en : std_logic := '0';
signal wr_data : std_logic_vector(63 downto 0) := (others => '0');
signal wr_done : std_logic := '0';
signal wr_accept : std_logic_vector(15 downto 0);
signal rd_clk : std_logic := '0';
signal rd_en : std_logic := '0';
signal rd_data : std_logic_vector(63 downto 0);
signal rd_valid : std_logic;
constant wr_clk_period : time := 10 ns;
constant rd_clk_period : time := 7 ns;
constant DATA_A : std_logic_vector(63 downto 0) := x"AAAAAAAAAAAAAAAA";
constant DATA_B : std_logic_vector(63 downto 0) := x"BBBBBBBBBBBBBBBB";
constant DATA_C : std_logic_vector(63 downto 0) := x"CCCCCCCCCCCCCCCC";
constant BUFF_1 : std_logic_vector (3 downto 0) := x"1";
constant BUFF_2 : std_logic_vector (3 downto 0) := x"2";
constant BUFF_3 : std_logic_vector (3 downto 0) := x"3";
signal test_fail : std_logic := '0';
signal test_done : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: send_mux PORT MAP (
wr_clk => wr_clk,
wr_buff => wr_buff,
wr_en => wr_en,
wr_data => wr_data,
wr_done => wr_done,
wr_accept => wr_accept,
rd_clk => rd_clk,
rd_en => rd_en,
rd_data => rd_data,
rd_valid => rd_valid
);
-- Clock process definitions
wr_clk_process :process
begin
wr_clk <= '0';
wait for wr_clk_period/2;
wr_clk <= '1';
wait for wr_clk_period/2;
end process;
rd_clk_process :process
begin
rd_clk <= '0';
wait for rd_clk_period/2;
rd_clk <= '1';
wait for rd_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for wr_clk_period;
if rd_valid /= '0' or
wr_accept /= x"FFFF" then
test_fail <= '1';
end if;
wr_buff <= BUFF_1;
wr_en <= '1';
wr_data <= DATA_A;
wr_done <= '0';
wait for wr_clk_period;
if rd_valid /= '0' or
wr_accept /= x"FFFF" then
test_fail <= '1';
end if;
wr_buff <= BUFF_2;
wr_en <= '1';
wr_data <= DATA_A;
wr_done <= '0';
wait for wr_clk_period;
if rd_valid /= '0' or
wr_accept /= x"FFFF" then
test_fail <= '1';
end if;
wr_buff <= BUFF_3;
wr_en <= '1';
wr_data <= DATA_A;
wr_done <= '0';
wait for wr_clk_period;
if rd_valid /= '0' or
wr_accept /= x"FFFF" then
test_fail <= '1';
end if;
wr_buff <= BUFF_1;
wr_en <= '1';
wr_data <= DATA_B;
wr_done <= '0';
wait for wr_clk_period;
if rd_valid /= '0' or
wr_accept /= x"FFFF" then
test_fail <= '1';
end if;
wr_buff <= BUFF_1;
wr_en <= '0';
wr_data <= (others => '0');
wr_done <= '1';
wait for wr_clk_period;
if rd_valid /= '0' or
wr_accept /= x"FFFD" then
test_fail <= '1';
end if;
wr_buff <= BUFF_1;
wr_en <= '0';
wr_data <= (others => '0');
wr_done <= '0';
wait until rd_valid = '1';
wait for rd_clk_period / 2;
if rd_valid /= '1' or
rd_data /= DATA_A or
wr_accept /= x"FFFD" then
test_fail <= '1';
end if;
rd_en <= '1';
wait for rd_clk_period;
if rd_valid /= '1' or
rd_data /= DATA_B or
wr_accept /= x"FFFD" then
test_fail <= '1';
end if;
rd_en <= '1';
wait for rd_clk_period;
if rd_valid /= '0' or
wr_accept /= x"FFFD" then
test_fail <= '1';
end if;
rd_en <= '0';
wait until wr_accept(1) = '1';
report "done";
test_done <= '1';
wait;
end process;
END;
|
