path: root/netfpga10g/hdl/system_loop.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;

entity system_loop is
generic (
        BUFF_COUNT : integer := 16;
        BUFF_BITS : integer := 4 -- 2^4 = 16
);
port (
        eth_clk : in std_logic;
        pcie_clk : in  std_logic;

        rx_frame : in std_logic_vector(63 downto 0);
        rx_sof : in std_logic;
        rx_eof : in std_logic;
        rx_valid : in std_logic;
        rx_bar0 : in std_logic;

        tx_frame : out std_logic_vector(63 downto 0);
        tx_sof : out std_logic;
        tx_eof : out std_logic;
        tx_half : out std_logic;
        tx_valid : out std_logic;
        tx_ready : in std_logic;

        interrupt : out std_logic;
        interrupt_rdy : in std_logic;

        max_read : in std_logic_vector(2 downto 0);
        max_write : in std_logic_vector(2 downto 0);

        local : in std_logic_vector(15 downto 0);

        xgmii_rxd : in std_logic_vector(63 downto 0);
        xgmii_rxc : in std_logic_vector(7 downto 0);

        xgmii_txd : out std_logic_vector(63 downto 0);
        xgmii_txc : out std_logic_vector(7 downto 0);

        mdio_command : out std_logic_vector(0 to 27);
        mdio_data : in std_logic_vector(0 to 15);
        mdio_enable : out std_logic;
        mdio_done : in std_logic
);
end system_loop;

architecture arch of system_loop is
        -- send mux
        signal send_rd_en : std_logic;
        signal send_rd_data : std_logic_vector (63 downto 0);
        signal send_rd_valid : std_logic;

        signal send_wr_buff : std_logic_vector (BUFF_BITS - 1 downto 0) := (others => '0');
        signal send_wr_en : std_logic := '0';
        signal send_wr_data : std_logic_vector (63 downto 0) := (others => '0');
        signal send_wr_done : std_logic := '0';
        signal send_wr_cancel : std_logic_vector (BUFF_COUNT - 1 downto 0);
        signal send_wr_accept : std_logic_vector (BUFF_COUNT - 1 downto 0);

        -- recv mux
        signal recv_wr_en : std_logic;
        signal recv_wr_data : std_logic_vector (63 downto 0);
        signal recv_wr_done : std_logic;
        signal recv_wr_accept : std_logic;

        signal recv_rd_buff : std_logic_vector (BUFF_BITS - 1 downto 0) := (others => '0');
        signal recv_rd_en : std_logic := '0';
        signal recv_rd_data : std_logic_vector (63 downto 0);
        signal recv_rd_length : std_logic_vector (8 downto 0);
        signal recv_rd_valid : std_logic_vector (BUFF_COUNT - 1 downto 0);

        -- pcie_rx
        signal rx_read : std_logic;
        signal rx_write : std_logic;
        signal rx_complete : std_logic;
        signal rx_data : std_logic_vector(63 downto 0);
        signal rx_address : std_logic_vector(63 downto 3);
        signal rx_tag : std_logic_vector(4 downto 0);

        signal remote : std_logic_vector(23 downto 0);

        -- pcie_tx
        signal tx_read : std_logic;
        signal tx_write : std_logic;
        signal tx_complete : std_logic;
        signal tx_data : std_logic_vector(63 downto 0);
        signal tx_address : std_logic_vector(63 downto 3);
        signal tx_length : std_logic_vector(8 downto 0);
        signal tx_tag : std_logic_vector(4 downto 0);
        signal tx_accept : std_logic;
        signal tx_done : std_logic;
begin
        eth_rx : entity work.eth_rx port map (
                clk => eth_clk,

                wr_en => recv_wr_en,
                wr_data => recv_wr_data,
                wr_done => recv_wr_done,
                wr_accept => recv_wr_accept,

                xgmii_rxd => xgmii_rxd,
                xgmii_rxc => xgmii_rxc
        );

        eth_tx : entity work.eth_tx port map (
                clk => eth_clk,

                rd_en => send_rd_en,
                rd_data => send_rd_data,
                rd_valid => send_rd_valid,

                xgmii_txd => xgmii_txd,
                xgmii_txc => xgmii_txc
        );

        send_mux : entity work.send_mux
        generic map (
                BUFF_COUNT => BUFF_COUNT,
                BUFF_BITS => BUFF_BITS
        )
        port map (
                wr_clk => pcie_clk,
                wr_buff => send_wr_buff,
                wr_en => send_wr_en,
                wr_data => send_wr_data,
                wr_done => send_wr_done,
                wr_cancel => send_wr_cancel,
                wr_accept => send_wr_accept,

                rd_clk => eth_clk,
                rd_en => send_rd_en,
                rd_data => send_rd_data,
                rd_valid => send_rd_valid
        );

        recv_mux : entity work.recv_mux
        generic map (
                BUFF_COUNT => BUFF_COUNT,
                BUFF_BITS => BUFF_BITS
        )
        port map (
                rd_clk => pcie_clk,
                rd_buff => recv_rd_buff,
                rd_en => recv_rd_en,
                rd_data => recv_rd_data,
                rd_length => recv_rd_length,
                rd_valid => recv_rd_valid,

                wr_clk => eth_clk,
                wr_en => recv_wr_en,
                wr_data => recv_wr_data,
                wr_done => recv_wr_done,
                wr_accept => recv_wr_accept
        );

        engine : entity work.engine
        generic map (
                BUFF_COUNT => BUFF_COUNT,
                BUFF_BITS => BUFF_BITS
        )
        port map (
                clk => pcie_clk,

                rd_buff => recv_rd_buff,
                rd_en => recv_rd_en,
                rd_data => recv_rd_data,
                rd_length => recv_rd_length,
                rd_valid => recv_rd_valid,

                wr_buff => send_wr_buff,
                wr_en => send_wr_en,
                wr_data => send_wr_data,
                wr_done => send_wr_done,
                wr_cancel => send_wr_cancel,
                wr_accept => send_wr_accept,

                rx_read => rx_read,
                rx_write => rx_write,
                rx_complete => rx_complete,
                rx_data => rx_data,
                rx_address => rx_address,
                rx_tag => rx_tag,

                tx_read => tx_read,
                tx_write => tx_write,
                tx_complete => tx_complete,
                tx_data => tx_data,
                tx_address => tx_address,
                tx_length => tx_length,
                tx_tag => tx_tag,
                tx_accept => tx_accept,
                tx_done => tx_done,

                interrupt => interrupt,
                interrupt_rdy => interrupt_rdy,

                max_read => max_read,
                max_write => max_write,

                mdio_command => mdio_command,
                mdio_data => mdio_data,
                mdio_enable => mdio_enable,
                mdio_done => mdio_done
        );

        pcie_rx : entity work.pcie_rx port map (
                clk => pcie_clk,

                frame => rx_frame,
                sof => rx_sof,
                eof => rx_eof,
                valid => rx_valid,

                read => rx_read,
                write => rx_write,
                complete => rx_complete,
                data => rx_data,
                address => rx_address,
                tag => rx_tag,
                remote => remote,

                bar0 => rx_bar0
        );

        pcie_tx : entity work.pcie_tx port map (
                clk => pcie_clk,

                frame => tx_frame,
                sof => tx_sof,
                eof => tx_eof,
                half => tx_half,
                valid => tx_valid,
                ready => tx_ready,

                read => tx_read,
                write => tx_write,
                complete => tx_complete,
                data => tx_data,
                address => tx_address,
                length => tx_length,
                tag => tx_tag,
                local => local,
                remote => remote,
                accept => tx_accept,
                done => tx_done
        );

end arch;