1 files changed, 199 insertions, 0 deletions
diff --git a/netfpga10g/tests/send_mux_test.vhd b/netfpga10g/tests/send_mux_test.vhd
new file mode 100644
index 0000000..f737ca9
--- /dev/null
+++ b/netfpga10g/tests/send_mux_test.vhd
@@ -0,0 +1,199 @@
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+ 
+ENTITY send_mux_test IS
+END send_mux_test;
+ 
+ARCHITECTURE behavior OF send_mux_test IS
+ 
+    COMPONENT send_mux
+    PORT(
+         wr_clk : IN  std_logic;
+         wr_buff : IN  std_logic_vector(3 downto 0);
+         wr_en : IN  std_logic;
+         wr_data : IN  std_logic_vector(63 downto 0);
+         wr_done : IN  std_logic;
+         wr_accept : OUT  std_logic_vector(15 downto 0);
+         rd_clk : IN  std_logic;
+         rd_en : IN  std_logic;
+         rd_data : OUT  std_logic_vector(63 downto 0);
+         rd_valid : OUT  std_logic
+        );
+    END COMPONENT;
+    
+   signal wr_clk : std_logic := '0';
+   signal wr_buff : std_logic_vector(3 downto 0) := (others => '0');
+   signal wr_en : std_logic := '0';
+   signal wr_data : std_logic_vector(63 downto 0) := (others => '0');
+   signal wr_done : std_logic := '0';
+   signal wr_accept : std_logic_vector(15 downto 0);
+   
+   signal rd_clk : std_logic := '0';
+   signal rd_en : std_logic := '0';
+   signal rd_data : std_logic_vector(63 downto 0);
+   signal rd_valid : std_logic;
+
+   constant wr_clk_period : time := 10 ns;
+   constant rd_clk_period : time := 7 ns;
+   
+   constant DATA_A : std_logic_vector(63 downto 0) := x"AAAAAAAAAAAAAAAA";
+   constant DATA_B : std_logic_vector(63 downto 0) := x"BBBBBBBBBBBBBBBB";
+   constant DATA_C : std_logic_vector(63 downto 0) := x"CCCCCCCCCCCCCCCC";
+   
+   constant BUFF_1 : std_logic_vector (3 downto 0) := x"1";
+   constant BUFF_2 : std_logic_vector (3 downto 0) := x"2";
+   constant BUFF_3 : std_logic_vector (3 downto 0) := x"3";
+   
+   signal test_fail : std_logic := '0';
+   signal test_done : std_logic := '0';
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: send_mux PORT MAP (
+          wr_clk => wr_clk,
+          wr_buff => wr_buff,
+          wr_en => wr_en,
+          wr_data => wr_data,
+          wr_done => wr_done,
+          wr_accept => wr_accept,
+          rd_clk => rd_clk,
+          rd_en => rd_en,
+          rd_data => rd_data,
+          rd_valid => rd_valid
+        );
+
+   -- Clock process definitions
+   wr_clk_process :process
+   begin
+		wr_clk <= '0';
+		wait for wr_clk_period/2;
+		wr_clk <= '1';
+		wait for wr_clk_period/2;
+   end process;
+ 
+   rd_clk_process :process
+   begin
+		rd_clk <= '0';
+		wait for rd_clk_period/2;
+		rd_clk <= '1';
+		wait for rd_clk_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin
+        wait for wr_clk_period;
+        
+        if rd_valid /= '0' or
+           wr_accept /= x"FFFF" then
+                test_fail <= '1';
+        end if;
+        
+        wr_buff <= BUFF_1;
+        wr_en <= '1';
+        wr_data <= DATA_A;
+        wr_done <= '0';
+        
+        wait for wr_clk_period;
+        
+        if rd_valid /= '0' or
+           wr_accept /= x"FFFF" then
+                test_fail <= '1';
+        end if;
+        
+        wr_buff <= BUFF_2;
+        wr_en <= '1';
+        wr_data <= DATA_A;
+        wr_done <= '0';
+        
+        wait for wr_clk_period;
+        
+        if rd_valid /= '0' or
+           wr_accept /= x"FFFF" then
+                test_fail <= '1';
+        end if;
+        
+        wr_buff <= BUFF_3;
+        wr_en <= '1';
+        wr_data <= DATA_A;
+        wr_done <= '0';
+        
+        wait for wr_clk_period;
+        
+        if rd_valid /= '0' or
+           wr_accept /= x"FFFF" then
+                test_fail <= '1';
+        end if;
+        
+        wr_buff <= BUFF_1;
+        wr_en <= '1';
+        wr_data <= DATA_B;
+        wr_done <= '0';
+        
+        wait for wr_clk_period;
+        
+        if rd_valid /= '0' or
+           wr_accept /= x"FFFF" then
+                test_fail <= '1';
+        end if;
+        
+        wr_buff <= BUFF_1;
+        wr_en <= '0';
+        wr_data <= (others => '0');
+        wr_done <= '1';
+        
+        wait for wr_clk_period;
+        
+        if rd_valid /= '0' or
+           wr_accept /= x"FFFD" then
+                test_fail <= '1';
+        end if;
+        
+        wr_buff <= BUFF_1;
+        wr_en <= '0';
+        wr_data <= (others => '0');
+        wr_done <= '0';
+        
+        wait until rd_valid = '1';
+        wait for rd_clk_period / 2;
+        
+        if rd_valid /= '1' or
+           rd_data /= DATA_A or
+           wr_accept /= x"FFFD" then
+                test_fail <= '1';
+        end if;
+        
+        rd_en <= '1';
+        
+        wait for rd_clk_period;
+        
+        if rd_valid /= '1' or
+           rd_data /= DATA_B or
+           wr_accept /= x"FFFD" then
+                test_fail <= '1';
+        end if;
+        
+        rd_en <= '1';
+        
+        wait for rd_clk_period;
+        
+        if rd_valid /= '0' or
+           wr_accept /= x"FFFD" then
+                test_fail <= '1';
+        end if;
+        
+        rd_en <= '0';
+        
+        wait until wr_accept(1) = '1';
+        
+        report "done";
+        test_done <= '1';
+        
+        wait;
+   end process;
+
+END;