1 files changed, 151 insertions, 0 deletions
diff --git a/netfpga10g/tests/buff_test.vhd b/netfpga10g/tests/buff_test.vhd
new file mode 100644
index 0000000..d9f4a0a
--- /dev/null
+++ b/netfpga10g/tests/buff_test.vhd
@@ -0,0 +1,151 @@
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+ 
+ENTITY buff_test IS
+END buff_test;
+ 
+ARCHITECTURE behavior OF buff_test IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT buff
+    PORT(
+         wr_clk : IN  std_logic;
+         wr_en : IN  std_logic;
+         wr_data : IN  std_logic_vector(63 downto 0);
+         wr_done : IN  std_logic;
+         wr_accept : OUT  std_logic;
+         rd_clk : IN  std_logic;
+         rd_en : IN  std_logic;
+         rd_data : OUT  std_logic_vector(63 downto 0);
+         rd_length : OUT  std_logic_vector(8 downto 0);
+         rd_valid : OUT  std_logic
+        );
+    END COMPONENT;
+    
+
+   signal wr_clk : std_logic := '0';
+   signal wr_en : std_logic := '0';
+   signal wr_data : std_logic_vector(63 downto 0) := (others => '0');
+   signal wr_done : std_logic := '0';
+   signal wr_accept : std_logic;
+   
+   signal rd_clk : std_logic := '0';
+   signal rd_en : std_logic := '0';
+   signal rd_data : std_logic_vector(63 downto 0);
+   signal rd_length : std_logic_vector(8 downto 0);
+   signal rd_valid : std_logic;
+
+   -- Clock period definitions
+   constant wr_clk_period : time := 10 ns;
+   constant rd_clk_period : time := 7 ns;
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: buff PORT MAP (
+          wr_clk => wr_clk,
+          wr_en => wr_en,
+          wr_data => wr_data,
+          wr_done => wr_done,
+          wr_accept => wr_accept,
+          rd_clk => rd_clk,
+          rd_en => rd_en,
+          rd_data => rd_data,
+          rd_length => rd_length,
+          rd_valid => rd_valid
+        );
+
+   -- Clock process definitions
+   wr_clk_process :process
+   begin
+		wr_clk <= '0';
+		wait for wr_clk_period/2;
+		wr_clk <= '1';
+		wait for wr_clk_period/2;
+   end process;
+ 
+   rd_clk_process :process
+   begin
+		rd_clk <= '0';
+		wait for rd_clk_period/2;
+		rd_clk <= '1';
+		wait for rd_clk_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin
+        wait for wr_clk_period;
+        
+        wr_en <= '1';
+        wr_data <= x"0123456789ABCDEF";
+        
+        wait for wr_clk_period;
+        
+        wr_en <= '1';
+        wr_data <= x"FEDCBA9876543210";
+        
+        wait for wr_clk_period;
+        
+        wr_en <= '0';
+        wr_data <= x"0000000000000000";
+        wr_done <= '1';
+        
+        wait for wr_clk_period;
+        
+        wr_done <= '0';
+        
+        wait until wr_accept = '1';
+        wait for wr_clk_period / 2;
+        
+        wr_en <= '1';
+        wr_data <= x"AAAAAAAAAAAAAAAA";
+        wait for wr_clk_period;
+        wr_data <= x"BBBBBBBBBBBBBBBB";
+        wait for wr_clk_period;
+        wr_data <= x"CCCCCCCCCCCCCCCC";
+        wait for wr_clk_period;
+        wr_data <= x"DDDDDDDDDDDDDDDD";
+        wait for wr_clk_period;
+        wr_en <= '0';
+        wr_data <= x"0000000000000000";
+        wr_done <= '1';
+        wait for wr_clk_period;
+        wr_done <= '0';
+        
+        wait until wr_accept = '1';
+        wait for wr_clk_period / 2;
+        wait for wr_clk_period;
+        
+        wr_en <= '1';
+        wr_data <= x"0123456789ABCDEF";
+        wait for wr_clk_period;
+        wr_data <= x"FEDCBA9876543210";
+        wait for wr_clk_period;
+        wr_data <= x"0123456789ABCDEF";
+        wait for wr_clk_period;
+        wr_data <= x"FEDCBA9876543210";
+        wait for wr_clk_period;
+        
+        wr_en <= '0';
+        wr_data <= x"0000000000000000";
+        wr_done <= '1';
+        wait for wr_clk_period;
+        wr_done <= '0';
+   
+        wait;
+   end process;
+   
+   process
+   begin
+        rd_en <= '0';
+        wait for rd_clk_period;
+        rd_en <= '1';
+        wait for rd_clk_period * 2;
+   end process;
+
+END;