Add the linux device driver and netfpga files

This adds the device driver and netfpga files from the master thesis
(in Dutch) "Implementatie van de Recursive Internet Architecture op
een FPGA platform" by Alexander D'hoore.

1 files changed, 285 insertions, 0 deletions

diff --git a/netfpga10g/tests/system_loop_test.vhd b/netfpga10g/tests/system_loop_test.vhd
new file mode 100644
index 0000000..81a4f6e
--- /dev/null
+++ b/netfpga10g/tests/system_loop_test.vhd
@@ -0,0 +1,285 @@
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+ 
+ENTITY system_loop_test IS
+END system_loop_test;
+ 
+ARCHITECTURE behavior OF system_loop_test IS 
+ 
+        COMPONENT system_loop
+        PORT(
+                clk : IN  std_logic;
+                
+                rx_frame : IN  std_logic_vector(63 downto 0);
+                rx_sof : IN  std_logic;
+                rx_eof : IN  std_logic;
+                rx_valid : IN  std_logic;
+                rx_bar0 : IN  std_logic;
+                
+                tx_frame : OUT  std_logic_vector(63 downto 0);
+                tx_sof : OUT  std_logic;
+                tx_eof : OUT  std_logic;
+                tx_half : OUT  std_logic;
+                tx_valid : OUT  std_logic;
+                tx_ready : IN  std_logic;
+                
+                interrupt : OUT  std_logic;
+                interrupt_rdy : IN  std_logic;
+                max_read : IN  std_logic_vector(2 downto 0);
+                max_write : IN  std_logic_vector(2 downto 0);
+                local : IN  std_logic_vector(15 downto 0)
+        );
+        END COMPONENT;
+    
+        signal clk : std_logic := '0';
+        
+        signal rx_frame : std_logic_vector(63 downto 0) := (others => '0');
+        signal rx_sof : std_logic := '0';
+        signal rx_eof : std_logic := '0';
+        signal rx_valid : std_logic := '0';
+        signal rx_bar0 : std_logic := '0';
+        
+        signal tx_frame : std_logic_vector(63 downto 0);
+        signal tx_sof : std_logic;
+        signal tx_eof : std_logic;
+        signal tx_half : std_logic;
+        signal tx_valid : std_logic;
+        signal tx_ready : std_logic := '0';
+        
+        signal interrupt : std_logic;
+        signal interrupt_rdy : std_logic := '0';
+        
+        signal max_read : std_logic_vector(2 downto 0) := (others => '0');
+        signal max_write : std_logic_vector(2 downto 0) := (others => '0');
+        signal local : std_logic_vector(15 downto 0) := (others => '0');
+
+        constant clk_period : time := 10 ns;
+        
+        signal test_fail : std_logic := '0';
+        
+        constant LEN_1 : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(1, 9));
+        constant LEN_2 : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(2, 9));
+        constant LEN_3 : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(3, 9));
+        
+        constant TAG_1 : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(1, 5));
+        constant TAG_2 : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(2, 5));
+        constant TAG_3 : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(3, 5));
+        
+        constant ADDR_1 : std_logic_vector(63 downto 3) := std_logic_vector(to_unsigned(1, 61));
+        constant ADDR_2 : std_logic_vector(63 downto 3) := std_logic_vector(to_unsigned(2, 61));
+        constant ADDR_3 : std_logic_vector(63 downto 3) := std_logic_vector(to_unsigned(3, 61));
+        
+        constant DATA_A : std_logic_vector(63 downto 0) := x"AAAAAAAAAAAAAAAA";
+        constant DATA_B : std_logic_vector(63 downto 0) := x"BBBBBBBBBBBBBBBB";
+        constant DATA_C : std_logic_vector(63 downto 0) := x"CCCCCCCCCCCCCCCC";
+        
+        constant ID_A : std_logic_vector(15 downto 0) := x"AAAA";
+        constant ID_B : std_logic_vector(15 downto 0) := x"BBBB";
+        constant ID_C : std_logic_vector(15 downto 0) := x"CCCC";
+        
+        constant BUFF_1 : std_logic_vector(3 downto 0) := x"1";
+        constant BUFF_2 : std_logic_vector(3 downto 0) := x"2";
+        constant BUFF_3 : std_logic_vector(3 downto 0) := x"3";
+        
+        constant CMD_STATUS : std_logic_vector(1 downto 0) := "00";
+        constant CMD_SEND : std_logic_vector(1 downto 0) := "01";
+        constant CMD_RECV : std_logic_vector(1 downto 0) := "10";
+        constant CMD_MDIO : std_logic_vector(1 downto 0) := "11";
+        
+        constant FRAME_0 : std_logic_vector(63 downto 0) := (others => '0');
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: system_loop PORT MAP (
+          clk => clk,
+          rx_frame => rx_frame,
+          rx_sof => rx_sof,
+          rx_eof => rx_eof,
+          rx_valid => rx_valid,
+          rx_bar0 => rx_bar0,
+          tx_frame => tx_frame,
+          tx_sof => tx_sof,
+          tx_eof => tx_eof,
+          tx_half => tx_half,
+          tx_valid => tx_valid,
+          tx_ready => tx_ready,
+          interrupt => interrupt,
+          interrupt_rdy => interrupt_rdy,
+          max_read => max_read,
+          max_write => max_write,
+          local => local
+        );
+
+   -- Clock process definitions
+   clk_process :process
+   begin
+		clk <= '0';
+		wait for clk_period/2;
+		clk <= '1';
+		wait for clk_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+        variable bar_addr : std_logic_vector(31 downto 0);
+        variable bar_data : std_logic_vector(63 downto 0);
+        variable expect : std_logic_vector(63 downto 0);
+        variable remote : std_logic_vector(15 downto 0);
+   begin
+        -- local = A
+        -- remote = B
+        local <= ID_A;
+        remote := ID_B;
+        
+        -- always bar0
+        rx_bar0 <= '1';
+        
+        wait for clk_period;
+        
+        -- nothing
+        if tx_frame /= FRAME_0 or
+           tx_sof /= '0' or
+           tx_eof /= '0' or
+           tx_half /= '0' or
+           tx_valid /= '0' or
+           interrupt /= '0' then
+                test_fail <= '1';
+        end if;
+        
+        -- rx_write of 64 bits to bar
+        rx_frame <= "0" & "10" & "00000" & x"00" & x"0002" &
+                    remote & x"00" & x"0F";
+        rx_sof <= '1';
+        rx_eof <= '0';
+        rx_valid <= '1';
+        
+        wait for clk_period;
+        
+        -- nothing
+        if tx_frame /= FRAME_0 or
+           tx_sof /= '0' or
+           tx_eof /= '0' or
+           tx_half /= '0' or
+           tx_valid /= '0' or
+           interrupt /= '0' then
+                test_fail <= '1';
+        end if;
+        
+        -- rx_write:
+        --      bar_addr: cmd = SEND, buff = 2, len = 2
+        --      bar_data: addr = 2
+        bar_addr := (others => '0');
+        bar_addr(4 downto 3) := CMD_SEND;
+        bar_addr(8 downto 5) := BUFF_2;
+        bar_addr(18 downto 10) := LEN_2;
+        bar_data := ADDR_2 & "000";
+        
+        rx_frame <= bar_addr & bar_data(63 downto 32);
+        rx_sof <= '0';
+        rx_eof <= '0';
+        rx_valid <= '1';
+        
+        wait for clk_period;
+        
+        -- nothing
+        if tx_frame /= FRAME_0 or
+           tx_sof /= '0' or
+           tx_eof /= '0' or
+           tx_half /= '0' or
+           tx_valid /= '0' or
+           interrupt /= '0' then
+                test_fail <= '1';
+        end if;
+        
+        rx_frame <= bar_data(31 downto 0) & x"00000000";
+        rx_sof <= '0';
+        rx_eof <= '1';
+        rx_valid <= '1';
+        
+        wait for clk_period;
+        
+        -- nothing
+        if tx_frame /= FRAME_0 or
+           tx_sof /= '0' or
+           tx_eof /= '0' or
+           tx_half /= '0' or
+           tx_valid /= '0' or
+           interrupt /= '0' then
+                test_fail <= '1';
+        end if;
+        
+        rx_frame <= (others => '0');
+        rx_sof <= '0';
+        rx_eof <= '0';
+        rx_valid <= '0';
+        
+        wait for clk_period;
+        
+        -- nothing
+        if tx_frame /= FRAME_0 or
+           tx_sof /= '0' or
+           tx_eof /= '0' or
+           tx_half /= '0' or
+           tx_valid /= '0' or
+           interrupt /= '0' then
+                test_fail <= '1';
+        end if;
+        
+        wait for clk_period;
+        
+        -- tx_read: addr = 2, len = 2, tag = 2
+        expect := "0" & "00" & "00000" & x"00" & "000000" & LEN_2 & "0" &
+                  local & "000" & TAG_2 & x"FF";
+                  
+        if tx_frame /= expect or
+           tx_sof /= '1' or
+           tx_eof /= '0' or
+           tx_half /= '0' or
+           tx_valid /= '1' or
+           interrupt /= '0' then
+                test_fail <= '1';
+        end if;
+        
+        tx_ready <= '1';
+        
+        wait for clk_period;
+        
+        expect := ADDR_2(31 downto 3) & "000" & x"00000000";
+                  
+        if tx_frame /= expect or
+           tx_sof /= '0' or
+           tx_eof /= '1' or
+           tx_half /= '1' or
+           tx_valid /= '1' or
+           interrupt /= '0' then
+                test_fail <= '1';
+        end if;
+        
+        tx_ready <= '1';
+        
+        wait for clk_period;
+                
+        -- nothing
+        if tx_frame /= FRAME_0 or
+           tx_sof /= '0' or
+           tx_eof /= '0' or
+           tx_half /= '0' or
+           tx_valid /= '0' or
+           interrupt /= '0' then
+                test_fail <= '1';
+        end if;
+        
+        tx_ready <= '0';
+        
+        
+                    
+        
+        
+        wait;
+   end process;
+
+END;