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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:42:12 02/23/2017
-- Design Name:
-- Module Name: /home/alexander/Code/raptor2/hw/tests/queue_test.vhd
-- Project Name: raptor2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: queue
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY queue_test IS
END queue_test;
ARCHITECTURE behavior OF queue_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT queue
PORT(
clk : IN std_logic;
reset : IN std_logic;
in_data : IN std_logic_vector(63 downto 0);
in_valid : in std_logic;
in_end : IN std_logic;
in_cancel : IN std_logic;
out_data : OUT std_logic_vector(63 downto 0);
out_valid : OUT std_logic;
out_next : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal in_data : std_logic_vector(63 downto 0) := (others => '0');
signal in_valid : std_logic := '0';
signal in_end : std_logic := '0';
signal in_cancel : std_logic := '0';
signal out_next : std_logic := '0';
--Outputs
signal out_data : std_logic_vector(63 downto 0);
signal out_valid : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: queue PORT MAP (
clk => clk,
reset => reset,
in_data => in_data,
in_valid => in_valid,
in_end => in_end,
in_cancel => in_cancel,
out_data => out_data,
out_valid => out_valid,
out_next => out_next
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- TESTS
process begin
reset <= '1';
wait for 5 ns;
reset <= '0';
wait;
end process;
process begin
wait for clk_period * 2;
in_data <= x"AAAAAAAAAAAAAAAA";
in_valid <= '1';
wait for clk_period;
in_data <= x"BBBBBBBBBBBBBBBB";
in_valid <= '0';
wait for clk_period;
in_data <= x"CCCCCCCCCCCCCCCC";
in_valid <= '1';
wait for clk_period;
in_data <= x"DDDDDDDDDDDDDDDD";
in_valid <= '1';
in_end <= '1';
wait for clk_period;
in_valid <= '0';
in_end <= '0';
wait for clk_period * 2;
in_data <= x"AAAAAAAAAAAAAAAA";
in_valid <= '1';
wait for clk_period;
in_data <= x"BBBBBBBBBBBBBBBB";
in_valid <= '1';
wait for clk_period;
in_data <= x"CCCCCCCCCCCCCCCC";
in_valid <= '1';
wait for clk_period;
in_data <= x"DDDDDDDDDDDDDDDD";
in_valid <= '1';
in_cancel <= '1';
wait for clk_period;
in_valid <= '0';
in_cancel <= '0';
end process;
process begin
wait for clk_period * 15;
out_next <= '1';
wait for clk_period * 2;
out_next <= '0';
wait for clk_period * 2;
out_next <= '1';
end process;
END;
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