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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY eth_rx_test IS
END eth_rx_test;
ARCHITECTURE behavior OF eth_rx_test IS
COMPONENT eth_rx
PORT(
clk : IN std_logic;
wr_en : OUT std_logic;
wr_data : OUT std_logic_vector(63 downto 0);
wr_done : OUT std_logic;
wr_accept : IN std_logic;
xgmii_rxd : IN std_logic_vector(63 downto 0);
xgmii_rxc : IN std_logic_vector(7 downto 0)
);
END COMPONENT;
signal clk : std_logic := '0';
signal wr_en : std_logic;
signal wr_data : std_logic_vector(63 downto 0);
signal wr_done : std_logic;
signal wr_accept : std_logic := '0';
signal xgmii_rxd : std_logic_vector(63 downto 0) := (others => '0');
signal xgmii_rxc : std_logic_vector(7 downto 0) := (others => '0');
constant clk_period : time := 10 ns;
constant IDLE : std_logic_vector(7 downto 0) := x"07";
constant START : std_logic_vector(7 downto 0) := x"FB";
constant TERM : std_logic_vector(7 downto 0) := x"FD";
constant ERR : std_logic_vector(7 downto 0) := x"FE";
constant PRE : std_logic_vector(7 downto 0) := "01010101";
constant SFD : std_logic_vector(7 downto 0) := "11010101";
signal test_fail : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: eth_rx PORT MAP (
clk => clk,
wr_en => wr_en,
wr_data => wr_data,
wr_done => wr_done,
wr_accept => wr_accept,
xgmii_rxd => xgmii_rxd,
xgmii_rxc => xgmii_rxc
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
xgmii_rxd <= IDLE & IDLE & IDLE & IDLE & IDLE & IDLE & IDLE & IDLE;
xgmii_rxc <= "00000000";
wait for clk_period;
if wr_en /= '0' or
wr_data /= x"0000000000000000" or
wr_done /= '0' then
test_fail <= '1';
end if;
xgmii_rxd <= SFD & PRE & PRE & PRE & PRE & PRE & PRE & START;
xgmii_rxc <= "00000001";
wr_accept <= '1';
wait for clk_period;
if wr_en /= '0' or
wr_data /= x"0000000000000000" or
wr_done /= '0' then
test_fail <= '1';
end if;
xgmii_rxd <= x"EFCDAB8967452301";
xgmii_rxc <= "00000000";
wait for clk_period;
if wr_en /= '1' or
wr_data /= x"0123456789ABCDEF" or
wr_done /= '0' then
test_fail <= '1';
end if;
xgmii_rxd <= IDLE & IDLE & IDLE & IDLE & IDLE & IDLE & IDLE & TERM;
xgmii_rxc <= "11111111";
wait for clk_period;
if wr_done /= '1' then
test_fail <= '1';
end if;
xgmii_rxd <= IDLE & IDLE & IDLE & IDLE & IDLE & IDLE & IDLE & IDLE;
xgmii_rxc <= "11111111";
wait for clk_period;
if wr_en /= '0' or
wr_data /= x"0000000000000000" or
wr_done /= '0' then
test_fail <= '1';
end if;
xgmii_rxd <= SFD & PRE & PRE & PRE & PRE & PRE & PRE & START;
xgmii_rxc <= "00000001";
wr_accept <= '0';
wait for clk_period;
if wr_en /= '0' or
wr_data /= x"0000000000000000" or
wr_done /= '0' then
test_fail <= '1';
end if;
xgmii_rxd <= x"EFCDAB8967452301";
xgmii_rxc <= "00000000";
wait for clk_period;
if wr_en /= '0' or
wr_data /= x"0000000000000000" or
wr_done /= '0' then
test_fail <= '1';
end if;
xgmii_rxd <= SFD & PRE & PRE & PRE & PRE & PRE & PRE & START;
xgmii_rxc <= "00000001";
wr_accept <= '1';
wait for clk_period;
if wr_en /= '0' or
wr_data /= x"0000000000000000" or
wr_done /= '0' then
test_fail <= '1';
end if;
xgmii_rxd <= x"ABCDABCDABCDABCD";
xgmii_rxc <= "00000000";
wait for clk_period;
if wr_en /= '1' or
wr_data /= x"CDABCDABCDABCDAB" or
wr_done /= '0' then
test_fail <= '1';
end if;
xgmii_rxd <= IDLE & IDLE & IDLE & ERR & IDLE & IDLE & IDLE & IDLE;
xgmii_rxc <= "00010000";
wait for clk_period;
if wr_done /= '1' then
test_fail <= '1';
end if;
xgmii_rxd <= PRE & PRE & PRE & START & IDLE & IDLE & IDLE & IDLE;
xgmii_rxc <= "00011111";
wr_accept <= '1';
wait for clk_period;
if wr_en /= '0' or
wr_data /= x"0000000000000000" or
wr_done /= '0' then
test_fail <= '1';
end if;
xgmii_rxd <= x"67452311" & SFD & PRE & PRE & PRE;
xgmii_rxc <= "00000000";
wait for clk_period;
if wr_en /= '0' or
wr_data /= x"0000000000000000" or
wr_done /= '0' then
test_fail <= '1';
end if;
xgmii_rxd <= IDLE & IDLE & IDLE & TERM & x"EFCDAB89";
xgmii_rxc <= "11110000";
wait for clk_period;
if wr_en /= '1' or
wr_data /= x"1123456789ABCDEF" or
wr_done /= '0' then
test_fail <= '1';
end if;
xgmii_rxd <= IDLE & IDLE & IDLE & IDLE & IDLE & IDLE & IDLE & IDLE;
xgmii_rxc <= "11111111";
wait for clk_period;
if wr_done /= '1' then
test_fail <= '1';
end if;
wait;
end process;
END;
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