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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY eth_buff_loop_test IS
END eth_buff_loop_test;
ARCHITECTURE behavior OF eth_buff_loop_test IS
signal eth_clk : std_logic := '0';
signal pcie_clk: std_logic := '0';
signal eth_rd_en : std_logic := '0';
signal eth_rd_data : std_logic_vector(63 downto 0);
signal eth_rd_length : std_logic_vector(8 downto 0);
signal eth_rd_valid : std_logic;
signal eth_wr_en : std_logic := '0';
signal eth_wr_data : std_logic_vector(63 downto 0) := (others => '0');
signal eth_wr_done : std_logic := '0';
signal eth_wr_accept : std_logic;
signal pcie_rd_en : std_logic := '0';
signal pcie_rd_data : std_logic_vector(63 downto 0);
signal pcie_rd_length : std_logic_vector(8 downto 0);
signal pcie_rd_valid : std_logic;
signal pcie_wr_en : std_logic := '0';
signal pcie_wr_data : std_logic_vector(63 downto 0) := (others => '0');
signal pcie_wr_done : std_logic := '0';
signal pcie_wr_accept : std_logic;
constant eth_clk_period : time := 7 ns;
constant pcie_clk_period : time := 10 ns;
signal xgmii_data : std_logic_vector(63 downto 0);
signal xgmii_control : std_logic_vector(7 downto 0);
signal test_fail : std_logic := '0';
BEGIN
buff_tx : entity work.buff port map (
wr_clk => pcie_clk,
wr_en => pcie_wr_en,
wr_data => pcie_wr_data,
wr_done => pcie_wr_done,
wr_accept => pcie_wr_accept,
rd_clk => eth_clk,
rd_en => eth_rd_en,
rd_data => eth_rd_data,
rd_length => eth_rd_length,
rd_valid => eth_rd_valid
);
buff_rx : entity work.buff port map (
wr_clk => eth_clk,
wr_en => eth_wr_en,
wr_data => eth_wr_data,
wr_done => eth_wr_done,
wr_accept => eth_wr_accept,
rd_clk => pcie_clk,
rd_en => pcie_rd_en,
rd_data => pcie_rd_data,
rd_length => pcie_rd_length,
rd_valid => pcie_rd_valid
);
eth_rx: entity work.eth_rx port map(
clk => eth_clk,
wr_en => eth_wr_en,
wr_data => eth_wr_data,
wr_done => eth_wr_done,
wr_accept => eth_wr_accept,
xgmii_rxd => xgmii_data,
xgmii_rxc => xgmii_control
);
eth_tx: entity work.eth_tx port map (
clk => eth_clk,
rd_en => eth_rd_en,
rd_data => eth_rd_data,
rd_valid => eth_rd_valid,
xgmii_txd => xgmii_data,
xgmii_txc => xgmii_control
);
-- Clock process definitions
eth_clk_process : process
begin
eth_clk <= '0';
wait for eth_clk_period/2;
eth_clk <= '1';
wait for eth_clk_period/2;
end process;
pcie_clk_process :process
begin
pcie_clk <= '0';
wait for pcie_clk_period/2;
pcie_clk <= '1';
wait for pcie_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for pcie_clk_period;
if pcie_wr_accept /= '1' then
test_fail <= '1';
end if;
pcie_wr_en <= '1';
pcie_wr_data <= x"0123456789ABCDEF";
wait for pcie_clk_period;
pcie_wr_en <= '1';
pcie_wr_data <= x"AAAAAAAAAAAAAAAA";
wait for pcie_clk_period;
pcie_wr_en <= '0';
pcie_wr_data <= (others => '0');
pcie_wr_done <= '1';
wait for pcie_clk_period;
pcie_wr_done <= '0';
wait until pcie_rd_valid = '1';
wait for pcie_clk_period / 2;
if pcie_rd_data /= x"0123456789ABCDEF" or
pcie_rd_length /= "000000010" then
test_fail <= '1';
end if;
pcie_rd_en <= '1';
wait for pcie_clk_period;
if pcie_rd_data /= x"AAAAAAAAAAAAAAAA" then
test_fail <= '1';
end if;
pcie_rd_en <= '1';
wait for pcie_clk_period;
if pcie_rd_valid /= '0' or
pcie_rd_data /= x"0000000000000000" or
pcie_rd_length /= "000000000" then
test_fail <= '1';
end if;
pcie_rd_en <= '0';
wait for pcie_clk_period;
if pcie_rd_valid /= '0' or
pcie_rd_data /= x"0000000000000000" or
pcie_rd_length /= "000000000" then
test_fail <= '1';
end if;
wait;
end process;
END;
|
