diff options
Diffstat (limited to 'netfpga10g')
| -rw-r--r-- | netfpga10g/raptor.tcl | 403 |
1 files changed, 403 insertions, 0 deletions
diff --git a/netfpga10g/raptor.tcl b/netfpga10g/raptor.tcl new file mode 100644 index 0000000..58a4465 --- /dev/null +++ b/netfpga10g/raptor.tcl @@ -0,0 +1,403 @@ +# +# Project automation script for raptor +# +# Created for ISE version 14.7 +# +# This file contains several Tcl procedures (procs) that you can use to automate +# your project by running from xtclsh or the Project Navigator Tcl console. +# If you load this file (using the Tcl command: source raptor.tcl), then you can +# run any of the procs included here. +# +# This script is generated assuming your project has HDL sources. +# Several of the defined procs won't apply to an EDIF or NGC based project. +# If that is the case, simply remove them from this script. +# +# You may also edit any of these procs to customize them. See comments in each +# proc for more instructions. +# +# This file contains the following procedures: +# +# Top Level procs (meant to be called directly by the user): +# run_process: you can use this top-level procedure to run any processes +# that you choose to by adding and removing comments, or by +# adding new entries. +# rebuild_project: you can alternatively use this top-level procedure +# to recreate your entire project, and the run selected processes. +# +# Lower Level (helper) procs (called under in various cases by the top level procs): +# show_help: print some basic information describing how this script works +# add_source_files: adds the listed source files to your project. +# set_project_props: sets the project properties that were in effect when this +# script was generated. +# create_libraries: creates and adds file to VHDL libraries that were defined when +# this script was generated. +# set_process_props: set the process properties as they were set for your project +# when this script was generated. +# + +set myProject "raptor" +set myScript "raptor.tcl" + +# +# Main (top-level) routines +# +# run_process +# This procedure is used to run processes on an existing project. You may comment or +# uncomment lines to control which processes are run. This routine is set up to run +# the Implement Design and Generate Programming File processes by default. This proc +# also sets process properties as specified in the "set_process_props" proc. Only +# those properties which have values different from their current settings in the project +# file will be modified in the project. +# +proc run_process {} { + + global myScript + global myProject + + ## put out a 'heartbeat' - so we know something's happening. + puts "\n$myScript: running ($myProject)...\n" + + if { ! [ open_project ] } { + return false + } + + set_process_props + # + # Remove the comment characters (#'s) to enable the following commands + # process run "Synthesize" + # process run "Translate" + # process run "Map" + # process run "Place & Route" + # + set task "Implement Design" + if { ! [run_task $task] } { + puts "$myScript: $task run failed, check run output for details." + project close + return + } + + set task "Generate Programming File" + if { ! [run_task $task] } { + puts "$myScript: $task run failed, check run output for details." + project close + return + } + + puts "Run completed (successfully)." + project close + +} + +# +# rebuild_project +# +# This procedure renames the project file (if it exists) and recreates the project. +# It then sets project properties and adds project sources as specified by the +# set_project_props and add_source_files support procs. It recreates VHDL Libraries +# as they existed at the time this script was generated. +# +# It then calls run_process to set process properties and run selected processes. +# +proc rebuild_project {} { + + global myScript + global myProject + + project close + ## put out a 'heartbeat' - so we know something's happening. + puts "\n$myScript: Rebuilding ($myProject)...\n" + + set proj_exts [ list ise xise gise ] + foreach ext $proj_exts { + set proj_name "${myProject}.$ext" + if { [ file exists $proj_name ] } { + file delete $proj_name + } + } + + project new $myProject + set_project_props + add_source_files + create_libraries + puts "$myScript: project rebuild completed." + + run_process + +} + +# +# Support Routines +# + +# +proc run_task { task } { + + # helper proc for run_process + + puts "Running '$task'" + set result [ process run "$task" ] + # + # check process status (and result) + set status [ process get $task status ] + if { ( ( $status != "up_to_date" ) && \ + ( $status != "warnings" ) ) || \ + ! $result } { + return false + } + return true +} + +# +# show_help: print information to help users understand the options available when +# running this script. +# +proc show_help {} { + + global myScript + + puts "" + puts "usage: xtclsh $myScript <options>" + puts " or you can run xtclsh and then enter 'source $myScript'." + puts "" + puts "options:" + puts " run_process - set properties and run processes." + puts " rebuild_project - rebuild the project from scratch and run processes." + puts " set_project_props - set project properties (device, speed, etc.)" + puts " add_source_files - add source files" + puts " create_libraries - create vhdl libraries" + puts " set_process_props - set process property values" + puts " show_help - print this message" + puts "" +} + +proc open_project {} { + + global myScript + global myProject + + if { ! [ file exists ${myProject}.xise ] } { + ## project file isn't there, rebuild it. + puts "Project $myProject not found. Use project_rebuild to recreate it." + return false + } + + project open $myProject + + return true + +} +# +# set_project_props +# +# This procedure sets the project properties as they were set in the project +# at the time this script was generated. +# +proc set_project_props {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Setting project properties..." + + project set family "Virtex5" + project set device "xc5vtx240t" + project set package "ff1759" + project set speed "-2" + project set top_level_module_type "HDL" + project set synthesis_tool "XST (VHDL/Verilog)" + project set simulator "ISim (VHDL/Verilog)" + project set "Preferred Language" "VHDL" + project set "Enable Message Filtering" "false" + +} + + +# +# add_source_files +# +# This procedure add the source files that were known to the project at the +# time this script was generated. +# +proc add_source_files {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Adding sources to project..." + + xfile add "constraints.ucf" + xfile add "coregen/block_ram.ngc" + xfile add "coregen/block_ram.vhd" + xfile add "coregen/cmd_fifo.ngc" + xfile add "coregen/data_fifo.ngc" + xfile add "coregen/pcie_core/source/bram_common.v" + xfile add "coregen/pcie_core/source/cmm_decoder.v" + xfile add "coregen/pcie_core/source/cmm_errman_cnt_en.v" + xfile add "coregen/pcie_core/source/cmm_errman_cor.v" + xfile add "coregen/pcie_core/source/cmm_errman_cpl.v" + xfile add "coregen/pcie_core/source/cmm_errman_ftl.v" + xfile add "coregen/pcie_core/source/cmm_errman_ram4x26.v" + xfile add "coregen/pcie_core/source/cmm_errman_ram8x26.v" + xfile add "coregen/pcie_core/source/cmm_intr.v" + xfile add "coregen/pcie_core/source/extend_clk.v" + xfile add "coregen/pcie_core/source/pcie_blk_cf.v" + xfile add "coregen/pcie_core/source/pcie_blk_cf_arb.v" + xfile add "coregen/pcie_core/source/pcie_blk_cf_err.v" + xfile add "coregen/pcie_core/source/pcie_blk_cf_mgmt.v" + xfile add "coregen/pcie_core/source/pcie_blk_cf_pwr.v" + xfile add "coregen/pcie_core/source/pcie_blk_if.v" + xfile add "coregen/pcie_core/source/pcie_blk_ll.v" + xfile add "coregen/pcie_core/source/pcie_blk_ll_arb.v" + xfile add "coregen/pcie_core/source/pcie_blk_ll_credit.v" + xfile add "coregen/pcie_core/source/pcie_blk_ll_oqbqfifo.v" + xfile add "coregen/pcie_core/source/pcie_blk_ll_tx.v" + xfile add "coregen/pcie_core/source/pcie_blk_ll_tx_arb.v" + xfile add "coregen/pcie_core/source/pcie_blk_plus_ll_rx.v" + xfile add "coregen/pcie_core/source/pcie_blk_plus_ll_tx.v" + xfile add "coregen/pcie_core/source/pcie_clocking.v" + xfile add "coregen/pcie_core/source/pcie_core.v" + xfile add "coregen/pcie_core/source/pcie_ep.v" + xfile add "coregen/pcie_core/source/pcie_gt_wrapper.v" + xfile add "coregen/pcie_core/source/pcie_gt_wrapper_top.v" + xfile add "coregen/pcie_core/source/pcie_gtx_wrapper.v" + xfile add "coregen/pcie_core/source/pcie_mim_wrapper.v" + xfile add "coregen/pcie_core/source/pcie_reset_logic.v" + xfile add "coregen/pcie_core/source/pcie_soft_int.v" + xfile add "coregen/pcie_core/source/pcie_top.v" + xfile add "coregen/pcie_core/source/prod_fixes.v" + xfile add "coregen/pcie_core/source/sync_fifo.v" + xfile add "coregen/pcie_core/source/tlm_rx_data_snk.v" + xfile add "coregen/pcie_core/source/tlm_rx_data_snk_bar.v" + xfile add "coregen/pcie_core/source/tlm_rx_data_snk_mal.v" + xfile add "coregen/pcie_core/source/tlm_rx_data_snk_pwr_mgmt.v" + xfile add "coregen/pcie_core/source/tx_sync_gtp.v" + xfile add "coregen/pcie_core/source/tx_sync_gtx.v" + xfile add "coregen/ram_4kB.ngc" + xfile add "coregen/ram_4kB.vhd" + xfile add "coregen/simple_fifo.ngc" + xfile add "hdl/buff.vhd" + xfile add "hdl/dma.vhd" + xfile add "hdl/engine.vhd" + xfile add "hdl/eth.vhd" + xfile add "hdl/eth_rx.vhd" + xfile add "hdl/eth_tx.vhd" + xfile add "hdl/mdio.vhd" + xfile add "hdl/pcie.vhd" + xfile add "hdl/pcie_rx.vhd" + xfile add "hdl/pcie_tx.vhd" + xfile add "hdl/pcie_wrapper.vhd" + xfile add "hdl/port_fifo.vhd" + xfile add "hdl/recv_mux.vhd" + xfile add "hdl/rx_eth.vhd" + xfile add "hdl/send_mux.vhd" + xfile add "hdl/system_loop.vhd" + xfile add "hdl/top.vhd" + xfile add "hdl/tx_eth.vhd" + xfile add "hdl/xaui/xaui_top.vhd" + xfile add "hdl/xaui/xaui_v10_4.ngc" + xfile add "hdl/xaui/xaui_v10_4_block.vhd" + xfile add "hdl/xaui/xaui_v10_4_cc_2b_1skp.vhd" + xfile add "hdl/xaui/xaui_v10_4_chanbond_monitor.vhd" + xfile add "hdl/xaui/xaui_v10_4_rocketio_wrapper.vhd" + xfile add "hdl/xaui/xaui_v10_4_rocketio_wrapper_tile.vhd" + xfile add "hdl/xaui/xaui_v10_4_tx_sync.vhd" + xfile add "tests/buff_test.vhd" + xfile add "tests/engine_test.vhd" + xfile add "tests/eth_buff_loop_test.vhd" + xfile add "tests/eth_rx_test.vhd" + xfile add "tests/eth_tx_test.vhd" + xfile add "tests/pcie_rx_test.vhd" + xfile add "tests/pcie_tx_test.vhd" + xfile add "tests/queue_test.vhd" + xfile add "tests/send_mux_test.vhd" + xfile add "tests/system_loop_test.vhd" + + # Set the Top Module as well... + project set top "arch" "top" + + puts "$myScript: project sources reloaded." + +} ; # end add_source_files + +# +# create_libraries +# +# This procedure defines VHDL libraries and associates files with those libraries. +# It is expected to be used when recreating the project. Any libraries defined +# when this script was generated are recreated by this procedure. +# +proc create_libraries {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: Creating libraries..." + + + # must close the project or library definitions aren't saved. + project save + +} ; # end create_libraries + +# +# set_process_props +# +# This procedure sets properties as requested during script generation (either +# all of the properties, or only those modified from their defaults). +# +proc set_process_props {} { + + global myScript + + if { ! [ open_project ] } { + return false + } + + puts "$myScript: setting process properties..." + + project set "Reduce Control Sets" "Auto" -process "Synthesize - XST" + project set "Target UCF File Name" "/users/gsharma/raptor/netfpga10g/constraints.ucf" -process "Back-annotate Pin Locations" + project set "Enable Internal Done Pipe" "true" -process "Generate Programming File" + project set "LUT Combining" "Auto" -process "Synthesize - XST" + + puts "$myScript: project property values set." + +} ; # end set_process_props + +proc main {} { + + if { [llength $::argv] == 0 } { + show_help + return truever + } + + foreach option $::argv { + switch $option { + "show_help" { show_help } + "run_process" { run_process } + "rebuild_project" { rebuild_project } + "set_project_props" { set_project_props } + "add_source_files" { add_source_files } + "create_libraries" { create_libraries } + "set_process_props" { set_process_props } + default { puts "unrecognized option: $option"; show_help } + } + } +} + +if { $tcl_interactive } { + show_help +} else { + if {[catch {main} result]} { + puts "$myScript failed: $result." + } +} |