Add the linux device driver and netfpga files

This adds the device driver and netfpga files from the master thesis
(in Dutch) "Implementatie van de Recursive Internet Architecture op
een FPGA platform" by Alexander D'hoore.

1 files changed, 77 insertions, 0 deletions

diff --git a/netfpga10g/hdl/send_mux.vhd b/netfpga10g/hdl/send_mux.vhd
new file mode 100644
index 0000000..8d9f667
--- /dev/null
+++ b/netfpga10g/hdl/send_mux.vhd
@@ -0,0 +1,77 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity send_mux is
+generic (
+        BUFF_COUNT : integer := 16;
+        BUFF_BITS : integer := 4 -- 2^4 = 16
+);
+    Port ( wr_clk : in  STD_LOGIC;
+           wr_buff : in  STD_LOGIC_VECTOR (BUFF_BITS - 1 downto 0);
+           wr_en : in  STD_LOGIC;
+           wr_data : in  STD_LOGIC_VECTOR (63 downto 0);
+           wr_done : in  STD_LOGIC;
+           wr_cancel : in  STD_LOGIC_VECTOR (BUFF_COUNT - 1 downto 0);
+           wr_accept : out  STD_LOGIC_VECTOR (BUFF_COUNT - 1 downto 0) := (others => '0');
+           rd_clk : in  STD_LOGIC;
+           rd_en : in  STD_LOGIC;
+           rd_data : out  STD_LOGIC_VECTOR (63 downto 0) := (others => '0');
+           rd_valid : out  STD_LOGIC := '0');
+end send_mux;
+
+architecture arch of send_mux is
+        type rd_data_t is array (0 to BUFF_COUNT - 1) of std_logic_vector(63 downto 0);
+
+        signal wr_en_i : std_logic_vector(BUFF_COUNT - 1 downto 0) := (others => '0');
+        signal wr_done_i : std_logic_vector(BUFF_COUNT - 1 downto 0) := (others => '0');
+        
+        signal rd_en_i : std_logic_vector(BUFF_COUNT - 1 downto 0) := (others => '0');
+        signal rd_data_i : rd_data_t := (others => (others => '0'));
+        signal rd_valid_i : std_logic_vector(BUFF_COUNT - 1 downto 0) := (others => '0');
+        signal rd_buff : integer range 0 to BUFF_COUNT - 1 := 0;
+begin
+        send_gen: for i in 0 to BUFF_COUNT - 1 generate
+                send_buff : entity work.buff port map (
+                        wr_clk => wr_clk,
+                        wr_en => wr_en_i(i),
+                        wr_data => wr_data,
+                        wr_done => wr_done_i(i),
+                        wr_cancel => wr_cancel(i),
+                        wr_accept => wr_accept(i),
+
+                        rd_clk => rd_clk,
+                        rd_en => rd_en_i(i),
+                        rd_data => rd_data_i(i),
+                        rd_length => open,
+                        rd_valid => rd_valid_i(i)
+                );
+                
+                wr_en_i(i) <= wr_en when to_integer(unsigned(wr_buff)) = i else '0';
+                wr_done_i(i) <= wr_done when to_integer(unsigned(wr_buff)) = i else '0';
+                
+                rd_en_i(i) <= rd_en when rd_buff = i else '0';
+        end generate send_gen;
+        
+        rd_data <= rd_data_i(rd_buff);
+        rd_valid <= rd_valid_i(rd_buff);
+        
+        process (rd_clk)
+                variable tmp_buff : integer range 0 to BUFF_COUNT - 1;
+        begin
+                if rising_edge(rd_clk) then
+                        if rd_valid_i(rd_buff) = '0' then
+                                for i in 0 to BUFF_COUNT - 1 loop
+                                        tmp_buff := (i + rd_buff) mod BUFF_COUNT;
+                                        
+                                        if rd_valid_i(tmp_buff) = '1' then
+                                                rd_buff <= tmp_buff;
+                                                exit;
+                                        end if;
+                                end loop;
+                        end if;
+                end if;
+        end process;
+end arch;
+