library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity port_fifo is
generic (
        BITS : integer := 14
);
port (
        reset : in std_logic;

        rd_clk : in std_logic;
        rd_read : in std_logic;
        rd_data : out std_logic_vector(63 downto 0);
        rd_empty : out std_logic;
        rd_count : out std_logic_vector(BITS downto 0);

        wr_clk : in std_logic;
        wr_write : in std_logic;
        wr_data : in std_logic_vector(63 downto 0);
        wr_full : out std_logic;
        wr_count : out std_logic_vector(BITS downto 0)
);
end port_fifo;

architecture arch of port_fifo is

        component data_fifo port (
                rst : in std_logic;
                rd_clk : in std_logic;
                rd_en : in std_logic;
                dout : out std_logic_vector(63 downto 0);
                empty : out std_logic;
                rd_data_count : out std_logic_vector(BITS downto 0);
                wr_clk : in std_logic;
                wr_en : in std_logic;
                din : in std_logic_vector(63 downto 0);
                full : out std_logic;
                wr_data_count : out std_logic_vector(BITS downto 0)
        );
        end component;

        signal raw_read : std_logic;
        signal raw_data : std_logic_vector(63 downto 0);
        signal raw_empty : std_logic;
        signal raw_count : std_logic_vector(BITS downto 0);

        signal has_extra : std_logic;
        signal extra : std_logic_vector(63 downto 0);
begin
        rd_data <= extra when has_extra = '1' and rd_read = '0' else raw_data;
        rd_empty <= '0' when has_extra = '1' and rd_read = '0' else '1';
        rd_count <= std_logic_vector(unsigned(raw_count) + 1) when has_extra = '1' and rd_read = '0' else raw_count;

        raw_read <= '0' when has_extra = '1' and rd_read = '0' else '1';

        process (rd_clk, reset)
        begin
                if reset = '1' then
                        has_extra <= '0';
                        extra <= (others => '0');

                elsif rising_edge(rd_clk) then
                        if has_extra = '1' then
                                if rd_read = '1' then
                                        has_extra <= not raw_empty;
                                        extra <= raw_data;
                                end if;
                        else
                                if rd_read = '0' then
                                        has_extra <= not raw_empty;
                                        extra <= raw_data;
                                end if;
                        end if;
                end if;
        end process;

        fifo : data_fifo port map (
                rst => reset,

                rd_clk => rd_clk,
                rd_en => raw_read,
                dout => raw_data,
                empty => raw_empty,
                rd_data_count => raw_count,

                wr_clk => wr_clk,
                wr_en => wr_write,
                din => wr_data,
                full => wr_full,
                wr_data_count => wr_count
        );
end arch;