From d1a1059d748955ed93a8e87c437c7eae1258293c Mon Sep 17 00:00:00 2001 From: Alexander D'hoore Date: Fri, 15 Dec 2017 15:37:58 +0100 Subject: Add the linux device driver and netfpga files This adds the device driver and netfpga files from the master thesis (in Dutch) "Implementatie van de Recursive Internet Architecture op een FPGA platform" by Alexander D'hoore. --- netfpga10g/constraints.ucf | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 netfpga10g/constraints.ucf (limited to 'netfpga10g/constraints.ucf') diff --git a/netfpga10g/constraints.ucf b/netfpga10g/constraints.ucf new file mode 100644 index 0000000..9f16110 --- /dev/null +++ b/netfpga10g/constraints.ucf @@ -0,0 +1,52 @@ + +CONFIG PART = xc5vtx240tff1759-2; + +NET "clk25" LOC = "AJ25" | IOSTANDARD = LVCMOS33; +NET "clk100" LOC = "AN25" | IOSTANDARD = LVCMOS33; + +NET "clk25" TNM_NET=TNM_NET_CLK25; +TIMESPEC TS_CLK25 = PERIOD TNM_NET_CLK25 25 MHz; + +NET "clk100" TNM_NET=TNM_NET_CLK100; +TIMESPEC TS_CLK100 = PERIOD TNM_NET_CLK100 100 MHz; + +NET "led1" LOC = "AK25" | IOSTANDARD = LVCMOS33; +NET "led2" LOC = "AM24" | IOSTANDARD = LVCMOS33; +NET "led3" LOC = "AP20" | IOSTANDARD = LVCMOS33; + +# PCI express +NET "pcie_clk_p" LOC = "AT4"; +NET "pcie_clk_n" LOC = "AT3"; +INST "pcie_wrapper/pcie_clk_ibuf" DIFF_TERM = "TRUE"; + +INST "pcie_wrapper/ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTX_DUAL_X1Y5; +INST "pcie_wrapper/ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTX_DUAL_X1Y4; +INST "pcie_wrapper/ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" LOC = GTX_DUAL_X1Y3; +INST "pcie_wrapper/ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" LOC = GTX_DUAL_X1Y2; + +NET "clk125" TNM_NET=TNM_NET_CLK125; +TIMESPEC TS_CLK125 = PERIOD TNM_NET_CLK125 125 MHz; + +# mdio + +NET "phy_reset_n" LOC = "AR20" | IOSTANDARD = LVCMOS33; +NET "mdc" LOC = "AK23" | IOSTANDARD = LVCMOS33; +NET "mdio" LOC = "AL20" | IOSTANDARD = LVCMOS33; + +# xaui + +NET "xaui/txoutclk" TNM_NET="clk156_top"; +TIMESPEC "TS_clk156_top" = PERIOD "clk156_top" 156.25 MHz; + +NET "clk50" TNM_NET=DCLK_CLK; +TIMESPEC TS_DCLK_CLK = PERIOD DCLK_CLK 50 MHz; + +NET *xaui_block/rocketio_wrapper_i/tile1_rxrecclk0_i TNM_NET=clk156_rec; +TIMESPEC TS_clk156_rec = PERIOD clk156_rec 156.25MHz; + +INST xaui/xaui_block/rocketio_wrapper_i/tile0_xaui_v10_4_rocketio_wrapper_i/YES_REVERSE_LANES.gtx_dual_i LOC=GTX_DUAL_X1Y6; +INST xaui/xaui_block/rocketio_wrapper_i/tile1_xaui_v10_4_rocketio_wrapper_i/YES_REVERSE_LANES.gtx_dual_i LOC=GTX_DUAL_X1Y7; + +NET "xaui0_clk_p" LOC = "M4" ; +NET "xaui0_clk_n" LOC = "M3" ; + -- cgit v1.2.3