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-rw-r--r--netfpga10g/hdl/pcie.vhd268
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diff --git a/netfpga10g/hdl/pcie.vhd b/netfpga10g/hdl/pcie.vhd
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+++ b/netfpga10g/hdl/pcie.vhd
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+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity pcie is
+generic (
+ BITS : integer := 14
+);
+port (
+ pcie_clk_p : in std_logic;
+ pcie_clk_n : in std_logic;
+ reset25 : in std_logic;
+
+ clk125_out : out std_logic;
+ reset125_out : out std_logic;
+
+ pci_exp_rxn : in std_logic_vector(7 downto 0);
+ pci_exp_rxp : in std_logic_vector(7 downto 0);
+ pci_exp_txn : out std_logic_vector(7 downto 0);
+ pci_exp_txp : out std_logic_vector(7 downto 0);
+
+ port0_read : out std_logic;
+ port0_rd_data : in std_logic_vector(63 downto 0);
+ port0_rd_empty : in std_logic;
+ port0_rd_count : in std_logic_vector(BITS downto 0);
+
+ port0_write : out std_logic;
+ port0_wr_data : out std_logic_vector(63 downto 0);
+ port0_wr_full : in std_logic;
+ port0_wr_count : in std_logic_vector(BITS downto 0);
+
+ port1_read : out std_logic;
+ port1_rd_data : in std_logic_vector(63 downto 0);
+ port1_rd_empty : in std_logic;
+ port1_rd_count : in std_logic_vector(BITS downto 0);
+
+ port1_write : out std_logic;
+ port1_wr_data : out std_logic_vector(63 downto 0);
+ port1_wr_full : in std_logic;
+ port1_wr_count : in std_logic_vector(BITS downto 0);
+
+ port2_read : out std_logic;
+ port2_rd_data : in std_logic_vector(63 downto 0);
+ port2_rd_empty : in std_logic;
+ port2_rd_count : in std_logic_vector(BITS downto 0);
+
+ port2_write : out std_logic;
+ port2_wr_data : out std_logic_vector(63 downto 0);
+ port2_wr_full : in std_logic;
+ port2_wr_count : in std_logic_vector(BITS downto 0);
+
+ port3_read : out std_logic;
+ port3_rd_data : in std_logic_vector(63 downto 0);
+ port3_rd_empty : in std_logic;
+ port3_rd_count : in std_logic_vector(BITS downto 0);
+
+ port3_write : out std_logic;
+ port3_wr_data : out std_logic_vector(63 downto 0);
+ port3_wr_full : in std_logic;
+ port3_wr_count : in std_logic_vector(BITS downto 0);
+
+ mdio_command : out std_logic_vector(0 to 27);
+ mdio_data : in std_logic_vector(0 to 15);
+ mdio_enable : out std_logic;
+ mdio_done : in std_logic;
+
+ leds : out std_logic_vector(2 downto 0)
+);
+end pcie;
+
+architecture arch of pcie is
+ signal clk125 : std_logic;
+ signal reset125 : std_logic;
+
+ signal rx_frame : std_logic_vector(63 downto 0);
+ signal rx_sof : std_logic;
+ signal rx_eof : std_logic;
+ signal rx_valid : std_logic;
+
+ signal rx_read : std_logic;
+ signal rx_write : std_logic;
+ signal rx_complete : std_logic;
+ signal rx_data : std_logic_vector(63 downto 0);
+ signal rx_address : std_logic_vector(28 downto 0);
+
+ signal tx_frame : std_logic_vector(63 downto 0);
+ signal tx_sof : std_logic;
+ signal tx_eof : std_logic;
+ signal tx_half : std_logic;
+ signal tx_valid : std_logic;
+ signal tx_ready : std_logic;
+
+ signal tx_read : std_logic;
+ signal tx_write : std_logic;
+ signal tx_complete : std_logic;
+ signal tx_data : std_logic_vector(63 downto 0);
+ signal tx_address : std_logic_vector(28 downto 0);
+ signal tx_length : std_logic_vector(8 downto 0);
+ signal tx_accept : std_logic;
+ signal tx_done : std_logic;
+
+ signal bus_dev_func : std_logic_vector(15 downto 0);
+ signal transaction_id : std_logic_vector(23 downto 0);
+
+ signal max_read : std_logic_vector(2 downto 0);
+ signal max_write : std_logic_vector(2 downto 0);
+
+ signal interrupt : std_logic;
+ signal interrupt_rdy : std_logic;
+
+ signal bar0 : std_logic;
+begin
+ clk125_out <= clk125;
+ reset125_out <= reset125;
+
+ pcie_wrapper : entity work.pcie_wrapper port map (
+ pcie_clk_p => pcie_clk_p,
+ pcie_clk_n => pcie_clk_n,
+ reset25 => reset25,
+
+ clk125 => clk125,
+ reset125 => reset125,
+
+ pci_exp_rxn => pci_exp_rxn,
+ pci_exp_rxp => pci_exp_rxp,
+ pci_exp_txn => pci_exp_txn,
+ pci_exp_txp => pci_exp_txp,
+
+ rx_frame => rx_frame,
+ rx_sof => rx_sof,
+ rx_eof => rx_eof,
+ rx_valid => rx_valid,
+
+ tx_frame => tx_frame,
+ tx_sof => tx_sof,
+ tx_eof => tx_eof,
+ tx_half => tx_half,
+ tx_valid => tx_valid,
+ tx_ready => tx_ready,
+
+ bus_dev_func => bus_dev_func,
+
+ max_read => max_read,
+ max_write => max_write,
+
+ interrupt => interrupt,
+ interrupt_rdy => interrupt_rdy,
+
+ bar0 => bar0
+ );
+
+ pcie_rx : entity work.pcie_rx port map (
+ clk => clk125,
+ reset => reset125,
+
+ frame => rx_frame,
+ sof => rx_sof,
+ eof => rx_eof,
+ valid => rx_valid,
+
+ read => rx_read,
+ write => rx_write,
+ complete => rx_complete,
+ data => rx_data,
+ address => rx_address,
+
+ transaction_id => transaction_id,
+ bar0 => bar0
+ );
+
+ pcie_tx : entity work.pcie_tx port map (
+ clk => clk125,
+ reset => reset125,
+
+ frame => tx_frame,
+ sof => tx_sof,
+ eof => tx_eof,
+ half => tx_half,
+ valid => tx_valid,
+ ready => tx_ready,
+
+ read => tx_read,
+ write => tx_write,
+ complete => tx_complete,
+ data => tx_data,
+ address => tx_address,
+ length => tx_length,
+ accept => tx_accept,
+ done => tx_done,
+
+ transaction_id => transaction_id,
+ bus_dev_func => bus_dev_func
+ );
+
+ dma : entity work.dma port map (
+ clk => clk125,
+ reset => reset125,
+
+ rx_read => rx_read,
+ rx_write => rx_write,
+ rx_complete => rx_complete,
+ rx_data => rx_data,
+ rx_address => rx_address,
+
+ tx_read => tx_read,
+ tx_write => tx_write,
+ tx_complete => tx_complete,
+ tx_data => tx_data,
+ tx_address => tx_address,
+ tx_length => tx_length,
+ tx_accept => tx_accept,
+ tx_done => tx_done,
+
+ port0_read => port0_read,
+ port0_rd_data => port0_rd_data,
+ port0_rd_empty => port0_rd_empty,
+ port0_rd_count => port0_rd_count,
+
+ port0_write => port0_write,
+ port0_wr_data => port0_wr_data,
+ port0_wr_full => port0_wr_full,
+ port0_wr_count => port0_wr_count,
+
+ port1_read => port1_read,
+ port1_rd_data => port1_rd_data,
+ port1_rd_empty => port1_rd_empty,
+ port1_rd_count => port1_rd_count,
+
+ port1_write => port1_write,
+ port1_wr_data => port1_wr_data,
+ port1_wr_full => port1_wr_full,
+ port1_wr_count => port1_wr_count,
+
+ port2_read => port2_read,
+ port2_rd_data => port2_rd_data,
+ port2_rd_empty => port2_rd_empty,
+ port2_rd_count => port2_rd_count,
+
+ port2_write => port2_write,
+ port2_wr_data => port2_wr_data,
+ port2_wr_full => port2_wr_full,
+ port2_wr_count => port2_wr_count,
+
+ port3_read => port3_read,
+ port3_rd_data => port3_rd_data,
+ port3_rd_empty => port3_rd_empty,
+ port3_rd_count => port3_rd_count,
+
+ port3_write => port3_write,
+ port3_wr_data => port3_wr_data,
+ port3_wr_full => port3_wr_full,
+ port3_wr_count => port3_wr_count,
+
+ max_read => max_read,
+ max_write => max_write,
+
+ interrupt => interrupt,
+ interrupt_rdy => interrupt_rdy,
+
+ mdio_command => mdio_command,
+ mdio_data => mdio_data,
+ mdio_enable => mdio_enable,
+ mdio_done => mdio_done,
+
+ leds => leds
+ );
+end arch;
+